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? nec corporation 1991 description the m pd75116f offers high-speed operation (t cy = 1.91 m s) at a low supply voltage (v dd = 2.7 v) which is not possible with the m pd75116. it has the same functions as, and is pin compatible with, the m pd75116, allowing low voltage sets to be developed by making efficient use of previously developed and used software resources. note, however, that the operating voltage range is different from that of the m pd75116. a version of the m pd75116f with on-chip prom, the m pd75p116 * , is also available for evaluation during system development. * there are some differences in electrical specifications between the m pd75116f and the m pd75p116. functions are described in detail in the following users manual, which should be read when carrying out design work. m pd75116 users manual : iem-922 features m pd75116 low voltage high-speed operation product ? instruction execution time 4-bit single-chip microcomputer m pd75108f,75112f,75116f mos integrated circuit data sheet the mark h shows major revised points. document no. ic-2810b (o.d.no. ic-8224b) date published april 1994p printed in japan the information in this document is subject to change without notice. 1.91 m s , 15.3 m s (operation at 4.19 mhz) 2 m s, 4 m s, 32 m s (operation at 2 mhz) ta = C40 to +50 c ta = C40 to +60 c v dd = 2.7 to 5.0 v 1.91 m s , 15.3 m s (operation at 4.19 mhz) 2 m s, 4 m s, 32 m s (operation at 2 mhz) v dd = 2.8 to 5.0 v v dd = 4.5 to 5.0 v 0.95 m s, 1.91 m s, 15.3 m s (operation at 4.19 mhz) 43 systematically arranged instructions ? 8-bit data transfer, compare, operation and increment/decrement instructions ? geti instruction allowing any 2-byte or 3-byte instruction to be implemented in 1 byte wide range of input/output ports : 58 ports 3 on-chip 8-bit timer channels : synchronous/asynchronous (start/stop) 8-bit serial interface on chip programmable threshold port : 4-bit resolution 4 channels "unless there are any particular functional differences, the m pd75116f is described in this document as a representative product."
2 m pd75108f,75112f,75116f ordering information ordering code package quality grade m pd75108fgf- -3be 64-pin plastic qfp (14 12 mm) standard m pd75112fgf- -3be 64-pin plastic qfp (14 12 mm) standard m pd75116fgf- -3be 64-pin plastic qfp (14 20 mm) standard remarks : rom code number applications cordless telephone subsets, portable radio equipment, pager, etc. please refer to "quality grade on nec semiconductor devices" (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
3 m pd75108f,75112f,75116f overview of functions contents 43 0.95 m s, 1.91 m s, 15.3 m s (v dd = 4.5 to 5.0 v, 4.19 mhz operation) 2 m s, 4 m s, 32 m s (v dd = 2.7 to 5.0 v, 2 mhz operation) 3-stage switching capability 0.95 m s (operating at 4.5 to 5.0 v) 1.91 m s (operating at 2.7 v ) 8064 8 bits ( m pd75108f) 12160 8 bits ( m pd75112f) 16256 8 bits ( m pd75116f) 512 4 bits 4-bits 8 4 banks (memory mapping) 3 accumulators for different manipulated data lengths ? 1-bit accumulator (cy), 4Cbit acculumalor (a), 8-bit accumulator (xa) total 58 ? cmos input pins : 10 ? cmos input/output pins (led direct drive capability) : 32 ? middle-high voltage n-ch open-drain input/output pins : 12 (led direct drive capability, a pull-up resistor can be incorporated bit-wise.) ? comparator input pins (4-bit precision) : 4 ? 8-bit timer/event counter 2 ? 8-bit basic interval timer (watchdog timer applicable) ? 2 transfer modes ? serial transmission/reception modes ? serial reception mode ? lsb top/msb top switchable external : 3 internal : 4 external : 2 ? stop/halt mode ? various bit manipulation instructions (set, reset, test, boolean operation) ? 8-bit data transfer, comparison, operation, increment/decrement instructions ? 1-byte relative branch instruction ? geti instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte ? bit manipulation memory (bit sequential buffer) on chip ? 64-pin plastic qfp (14 20 mm) item basic instructions instruction cycle minimum instruction execution time on-chip memory general register accumulator input/output port timer/counter 8-bit serial interface vector interrupt test input standby instruction set others package rom ram
4 m pd75108f,75112f,75116f contents 1. pin configuration (top view) ..................................................................................................... 6 2. block diagram .................................................................................................................................. 7 3. pin functions .................................................................................................................................... 8 3.1 port pins ..................................................................................................................................................... 8 3.2 other pins ................................................................................................................................................... 9 3.3 pin input/output circuits ................................................................................................................... 10 3.4 recommended connection of unused pins ................................................................................. 11 3.5 precautions concerning p00/int4 pin and reset pin ............................................................... 12 4. memory configuration ................................................................................................................ 13 5. peripheral hardware functions .............................................................................................. 18 5.1 digital input/output ports ................................................................................................................ 18 5.2 clock generator ..................................................................................................................................... 19 5.3 clock output circuit ............................................................................................................................. 20 5.4 basic interval timer .............................................................................................................................. 21 5.5 timer/event counter ............................................................................................................................. 21 5.6 serial interface ....................................................................................................................................... 23 5.7 programmable threshold port (analog input port) ............................................................ 25 5.8 bit sequential buffer ........................................................................................................................... 26 6. interrupt function ........................................................................................................................ 27 7. standby function ........................................................................................................................... 29 8. reset function ................................................................................................................................. 30 9. instruction set ................................................................................................................................ 32 10. application example ...................................................................................................................... 41 10.1 cordless telephone (subset) ............................................................................................................ 41 10.2 display pager ............................................................................................................................................ 42 11. mask option selection .................................................................................................................. 43 12. electrical specifications ............................................................................................................ 44 12.1 when ta = C40 to +50 c, v dd = 2.7 to 5.0 v ........................................................................................... 45 12.2 when ta = C40 to +60 c, v dd = 2.8 to 5.0 v ........................................................................................... 55
5 m pd75108f,75112f,75116f 13. characteristic curves (reference) ......................................................................................... 65 14. package information ..................................................................................................................................... 71 15. recommended soldering conditions ..................................................................................... 73 appendix a. functional differences among m pd751 series products ....................... 74 appendix b. development tools ...................................................................................................... 76 appendix c. related documents ..................................................................................................... 77
m pd75108,75112f,75116f 6 1. pin configuration (top view) 64-pin plastic qfp (14 20 mm) m pd75116fgf- -3be m pd75112fgf- -3be m pd75116fgf- -3be h pin name p00-p03 : port 0 sck : serial clock p10-p13 : port 1 so : serial output p20-p23 : port 2 si : serial input p30-p33 : port 3 pto0, pto1 : programmable timer output p40-p43 : port 4 pcl : programmable clock p50-p53 : port 5 pth00-pth03 : programmable treshold input p60-p63 : port 6 int0, int1, int4 : external vectored interrupt input p70-p73 : port 7 int2, int3 : external test input p80-p83 : port 8 ti0, ti1 : timer input p90-p93 : port 9 x1, x2 : clock oscillation p120-p123 : port 12 reset : reset p130-p133 : port 13 nc : no connection p140-p143 : port 14 v dd : positive power supply v ss : ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x2 x1 p41 p40 p53 p52 p51 p50 reset p63 p62 p61 p60 p73 p72 20 21 22 23 24 25 26 27 28 29 30 31 32 64 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 p42 p43 p30 p31 p32 p33 v dd nc p141 p142 p143 p130 p81 p71 63 35 34 33 p131 p132 p133 p120 p121 p122 p123 p00/int4 p02/so p20/pto0 p23 p01/sck p03/si p21/pto1 p22/pcl t11 t10 pth00 pth01 17 18 19 p70 p83 p82 p80 p93 p92 p91 p90 v ss p13/int3 p12/int2 p11/int1 p10/int0 pth03 pth02 p140
m pd75108f,75112f,75116f 7 p ort 0 port 1 4 4 p00-p03 p10-p13 port 3 port 4 port 5 port 6 4 4 4 4 port 2 4 p20-p23 p30-p33 p40-p43 p50-p53 p60-p63 port 7 4 p70-p73 sp(8) bank general reg. ram data memory 512 4 bits decode and control cy alu program * counter reset v ss stand by control v dd cpu clock clock generator clock divider clock output control x2 x1 pcl/p22 f xx / 2 n basic interval timer inter- rupt control intt1 intbt port 14 4 p140-p143 port 12 4 p120-p123 timer/event counter #0 intt0 ti0 pto0/p20 timer/event counter #1 ti1 pto1/p21 serial interface intsio sck/p01 so/p02 si/p03 program- mable threshold port #0 pth00-pth03 int4/p00 int2/p12 int1/p11 int0/p10 int3/p13 port 13 4 p130-p133 port 9 4 p90-p93 port 8 4 p80-p83 bit seq. buffer (16) 4 f * the m pd75108f program counter is composed of 13 bits and the m pd75112f/75116f program counter is composed of 14 bits 2. block diagram rom program memory 8064 8 bits ( m pd75108f) 12160 8 bits ( m pd75112f) 16256 8 bits ( m pd75116f)
8 m pd75108f,75112f,75116f 4-bit input port (port 0). 4-bit input port (port 1). 4-bit input/output port (port 2). programmable 4-bit input/output port (port 3). input/output can be specified bit-wise. 4-bit input/output port (port 4). 4-bit input/output port (port 5). programmable 4-bit input/output port (port 6). input/output can be specified bit-wise. 4-bit input/output port (port 7). 4-bit input/output port (port 8). 4-bit input/output port (port 9). n-ch open-drain 4-bit input/output port (port 12). on-chip pull-up resistor can be specified bit-wise (mask option). open-drain: +10 v withstand voltage n-ch open-drain 4-bit input/output port (port 13). on-chip pull-up resistor can be specified bit-wise (mask option). open-drain: +10 v withstand voltage n-ch open-drain 4-bit input/output port (port 14). on-chip pull-up resistor can be specified bit-wise (mask option). open-drain: +10 v withstand voltage p00 p01 p02 p03 p10 p11 p12 p13 p20 *3 p21 *3 p22 *3 p23 *3 p30 to p33 *3 p40 to p43 *3 p50 to p53 *3 p60 to p63 *3 p70 to p73 *3 p80 to p83 *3 p90 to p93 *3 p120 to p123 *3 p130 to p133 *3 p140 to p143 *3 input input input input input input input input input input input *2 input *2 input *2 3. pin functions 3.1 port pins input input/output input/output input input input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output dual- function pin int4 sck so si int0 int1 int2 int3 pto0 pto1 pcl i/ocircuit type *1 b f e b b e e e e e e e e m m m *1. l l : schmitt trigger input 2 . open-drain high impedance on-chip pull-up resistor high level 3. direct led drive capability pin name input/output function 8-bit i/o after reset
9 m pd75108f,75112f,75116f pth00 to pth03 ti0 ti1 pto0 pto1 sck so si int4 int0 int1 int2 int3 pcl x1, x2 reset nc *2 v dd v ss 3.2 other pins input input input/output input/output input/output input input input input input/output input dual- function pin p20 p21 p01 p02 p03 p00 p10 p11 p12 p13 p22 i/o circuit type *1 n b e f e b b b b e b input input input input input input input input variable threshold voltage 4-bit analog input port. external event pulse input to timer/event counter. or edge detection vectored interrupt input or 1-bit input is also possible. timer/event counter output serial clock input/output serial data output serial data input edge detection vector interrupt input (detection of both rising and falling edges) edge detection vector interrupt input (detection edge se- lectable) edge detection testable input (rising edge detection) clock output system clock oscillation crystal/ceramic connection pin. when an external clock is used, the clock is input to x1 and the inverted clock is input to x2. system reset input (low-level active). no connection positive power supply gnd potential *1. l l : schmitt trigger input 2. when sharing a print board with m pd75p116, nc pin should be connected to v dd . after reset function input/output pin name
10 m pd75108f,75112f,75116f 3.3 pin input/output circuits the input/output circuits of each pin of the m pd75116f are shown in abbreviated form. fig. 3-1 pin input/output circuit list type a type f type b type d type e type m type n in/out data output disable type d p-ch v dd in n-ch in pull-up resistor v dd in/out n-ch (+6 v withstand voltage) data output disable (mask option) middle-high voltage input buffer (+6 v withstand voltage) in/out data output disable type d type a p-ch v dd out n-ch data output disable + v ref (threshold voltage) cmos standard input buffer this is an input/output circuit made up of a type d push-pull output and type b schmitt-triggered input. schmitt-trigger input with hysteresis characteristic push-pull output that can be made high- impedance output (p-ch and n-ch off) this is an input/output circuit made up of a type d push-pull output and type a input buffer. comparator type b
11 m pd75108f,75112f,75116f 3.4 recommended connection of unused pins pin pth00 to pth03 ti0 ti1 p00 p01 to p03 p10 to p13 p20 to p23 p30 to p33 p40 to p43 p50 to p53 p60 to p63 p70 to p73 p80 to p83 p90 to p93 p120 to p123 p130 to p133 p140 to p143 nc recommended connection connect to v ss or v dd . connect to v ss . connect to v ss or v dd . connect to v ss . input : connect to v ss or v dd . output : leave open. leave open * * if a printed board is used with the m pd75p116, nc pin should be connected to v dd directly.
12 m pd75108f,75112f,75116f 3.5 precautions concerning p00/int4 pin and reset pin in addition to the functions shown in 3.1 and 3.2, the p00/int4 pin and reset pin are also used to set the test mode for testing internal m pd75116f operation (for ic testing). the test mode is set when a voltage greater than v dd is applied to either of these pins. consequently, if noise exceeding v dd is applied during normal operation, the test mode may be entered, making it impossible for normal operation to continue. if, for example, inter-wiring noise is applied to the p00/int4 or reset pin due to the length of the wiring from these pins, and the pin voltage exceeds v dd , misoperation may result. wiring should therefore be carried out so that interwiring noise is suppressed as far as possible. if it is completely impossible to suppress noise, noise prevention measures should be taken using an external component as shown below. l l capacitor connected between p00/int4 or reset and v dd l l diode with small v f (0.3 v or less) connected between p00/int4 or reset and v dd v dd v dd p00/int4, reset diode with small v f v dd v dd p00/int4, reset
13 m pd75108f,75112f,75116f 4. memory configuration program memory (rom) : 8064 8 bits (0000h to 1f7fh) : m pd75108f 12160 8 bits (0000h to 2f7fh) : m pd75112f 16256 8 bits (0000h to 3f7fh) : m pd75116f ? 0000h to 0001h : vector table in which a program start address after reset is written. ? 0002h to 000bh : vector table in which program start addresses after interruption are written. ? 0020h to 007fh : table area referred by geti instruction data memory ? data area : 512 4 bits (000h to 1ffh) ? peripheral hardware area : 128 4 bits (f80h to fffh)
14 m pd75108f,75112f,75116f fig. 4-1 program memory map ( m pd75108f) remarks apart from the above instructions, branching is possible to an address at which only the pc low-order 8 bits have been changed by the br pcde or br pcxa instruction. mbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 76 0 address internal reset start address (high-order 5 bits) internal reset start address (low-order 8 bits) (high-order 5 bits) int0/int1 start address (high-order 5 bits) intbt/int4 start address (low-order 8 bits) int0/int1 start address (low-order 8 bits) intsio start address (high-order 5 bits) intsio start address (low-order 8 bits) intt0 start address (high-order 5 bits) intt0 start address (low-order 8 bits) intt1 start address (high-order 5 bits) intt1 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address br ! addr instruction branch address rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe 0fffh 1000h 1f7fh call ! addr instruction subroutine entry address br $ addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address by geti instruction brcb !caddr instruction branch address 0 0 0 0 0 0 intbt/int4 start address 5
15 m pd75108f,75112f,75116f fig. 4-2 program memory map ( m pd75112f) remarks apart from the above instructions, branching is possible to an address at which only the pc low-order 8 bits have been changed by the br pcde or br pcxa instruction. mbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 76 0 address internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) int0/int1 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0/int1 start address (low-order 8 bits) intsio start address (high-order 6 bits) intsio start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) intt1 start address (high-order 6 bits) intt1 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address br ! addr instruction branch address rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe 1fffh 2000h 2f7fh call ! addr instruction subroutine entry address br $ addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address by geti instruction brcb !caddr instruction branch address brcb !caddr instruction branch address
16 m pd75108f,75112f,75116f fig. 4-3 program memory map ( m pd75116f) remarks apart from the above instructions, branching is possible to an address at which only the pc low-order 8 bits have been changed by the br pcde or br pcxa instruction. mbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 76 0 address internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) int0/int1 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0/int1 start address (low-order 8 bits) intsio start address (high-order 6 bits) intsio start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) intt1 start address (high-order 6 bits) intt1 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address br ! addr instruction branch address rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe 1fffh 2000h 2fffh 3000h 3f7fh call ! addr instruction subroutine entry address br $ addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address by geti instruction brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address
17 m pd75108f,75112f,75116f fig. 4-4 data memory map 256 4 256 4 128 4 (32 4) bank 0 bank 1 bank 15 000h 01fh 0ffh 100h f80h fffh general register area stack area data area static ram (512 4) peripheral hardware area data memory memory bank not on-chip 1ffh
18 m pd75108f,75112f,75116f 5. peripheral hardware functions 5.1 digital input/output ports there are the following three digital input/output ports. ? cmos input (port0, port1) : 8 ? cmos input/output (port2 to port9) : 32 ? n-ch open-drain input/output (port12 to port14) : 12 total : 52 table 5-1 list of input/output pin manipulation commands port 0 port 1 port 3 port 6 port 2 port 4 port 5 port 7 port 8 port 9 port12 port13 port14 port name function operation/features remarks 4-bit input 4-bit input/output * 4-bit input/output * (n-ch open-drain +10 v withstand voltage) regardless of the operating mode of the shared pin, reading or test is always possible. can be set in the input or output bit-wise. can be set in the input or output mode as a 4- bit unit. ports 4 and 5, 6 and 7, and 8 and 9 are paired and data input/output is possible as an 8-bit unit. can be set to input or output mode as a 4-bit unit. ports 12 and 13 are paired and data input/ output is possible as an 8-bit unit. these pins are shared with si, so, sck, int0 to int4. port 2, pt00, pt01, and pcl share the same pins. on-chip pull-up resistor specifi- able bit-wise by mask option. * can drive a led directly.
19 m pd75108,75112f,75116f 5.2 clock generator (1) clock generator configuration this is the circuit which generates various kinds of clock supplied to the cpu and peripheral hardware to control the cpu operating mode. this circuit can also change the instruction execution time. 0.95 m s/1.91 m s/15.3 m s (4.19 mhz operation) fig. 5-1 clock generator block diagram remarks 1. f xx = crystal/ceramic oscillator frequency 2. f x = external clock frequency 3. f = cpu clock 4. * indicates instruction execution 5. pcc : processor clock control register 6. one f clock cycle (t cy ) is one machine cycle. see "ac characteristics" in 12. "electrical specifications" for t cy . x1 f xx or f x ? basic interval timer (bt) ? clock output circuit ? timer/event counter ? serial interface frequency divider 1/2 selector halt f/f wait release signal from bt reset signal standby release signal from interrupt control circuit stop f/f s r q pcc2, pcc3 clear oscil- lation stop pcc 4 internal bus system clock oscillation circuit s r q halt * stop * frequency divider 1/4 ?cpu ?clock output circuit f 1/16 x2 1/8 to 1/4096 pcc0 pcc1 pcc2 pcc3
20 m pd75108f,75112f,75116f 5.3 clock output circuit the clock output circuit is a circuit which outputs a clock pulse from p22/pcl and is used to supply clock pulses to remote control outputs or peripheral lsis. clock output (pcl) : f , 524 khz, 262 khz (4.19 mhz operation) fig. 5-2 configuration of clock output circuit clom3 clom1 clom0 4 internal bus clom p22 output latch port2.2 bit 2 of pmgb bit specified in port 2 input/output mode output buffer p22/pcl f xx /2 3 f xx /2 4 selector f from clock generator 0
21 m pd75108,75112f,75116f 5.4 basic interval timer the basic interval timer includes the following functions. it operates as an interval timer which generates reference time interrupts. it can be applied as a watchdog timer which detects when a program is out of control. selects and counts wait times when the standby mode is released. it reads count contents. fig. 5-3 basic interval timer configuration remarks * indicates instruction execution. internal bus f xx /2 5 f xx /2 7 f xx /2 12 from clock generator 4 btm3 btm2 btm1 btm0 btm mpx bt irqbt set bt interrupt request flag clear clear basic interval timer (8-bit frequency divider) wait release signal during standby release 8 3 vector interrupt request signal f xx /2 9 * set1 5.5 timer/event counter the m pd75116f incorporates two internal timer/event counter channels. timer/event counter channel 0 and channel 1 differ only in selectable count pulse (cp) and clock supply function to serial interface and are the same in other configurations and functions. the functions of the timer/event counter are as follows. operates as a programmable interval timer. outputs square waves in the desired frequency to the pton pin. operates as an event counter. use of tin pin as an external interrupt input pin. divides the tin pin input into n divisions and outputs it to the pton pin (frequency divider operation). supplies a serial shift clock to the serial interface circuit. (channel 0 only) count status read function.
22 m pd75108f,75112f,75116f fig. 5-4 timer/event counter block diagram (n = 0, 1) *1. set1 : instruction execution. 2. for details, see fig. 5-1. 3. the serial interface signal is output only from timer/event counter channel 0. from clock generator input buffer *2 mpx tmn6 set1 *1 tmn timer operation start cp count register (8) clear 8 comparator (8) 8 8 modulo register (8) 8 8 internal bus tmodn match tout f/f toen to enable flag p2n output latch port2.n bit 2 of pgmb port 2 input/ output mode to serial interface *3 p2n/pton output buffer inttn (irqtn set signal) irqtn clear signal tn tin tin tmn7 tmn5 tmn4 tmn3 tmn2 tmn1 tmn0 ton to selector edge detector tmn0 reset tmn1 tofn
23 m pd75108,75112f,75116f 5.6 serial interface the m pd75116f incorporates the clocked 8-bit serial interface. there are the following two modes of serial interface. ? 3-wire serial i/o mode (msb-first/lsb-first switchable) ? operation stop mode in the 3-wire serial i/o mode, the m pd75116f can be connected with the 75x series, 78k series and various kinds of i/o devices.
24 m pd75108f,75112f,75116f * set1 : instruction execution fig. 5-5 serial interface block diagram shift registor (8) serial clock counter (3) clear overflow serial start siom7 siom6 siom5 siom4 siom3 siom2 siom1 siom0 siom set1 * 8 8 8 p03/si p02/so p01/sck sio7 sio sio0 irqsio clear signal tof0 (from timer channel 0) f xx /2 10 f xx /2 4 f mpx r s q internal bus intsio irqsio set signal
25 m pd75108,75112f,75116f 5.7 programmable threshold port (analog input port) the m pd75116f is provided with 4-bit analog input pins (pth00 to pth03) for which the threshold voltage can be changed. these pins have a configuration as shown in fig. 5-6. the threshold voltage (v ref ) can be selected in 16 ways (v dd v dd ) and analog signals can be directly input. this port can also be used as a digital signal input port by selecting v dd 7.5/16 as v ref . fig. 5-6 programmable threshold port block diagram 16 16 0.5 15.5 pthm7 pthm6 pthm5 pthm4 pthm3 pthm2 pthm1 pthm0 pthm 4 mpx v ref v dd pth00 pth01 pth02 pth03 + - + - + - + - operation stopped pth0 input buffer programmable threshold port input latch (4) internal bus 8 2 1 r 2 1 r r r
26 m pd75108f,75112f,75116f 5.8 bit sequential buffer 16 bits bit manipulation of the bit sequential buffer is the bit manipulation special data memory. since, in particular, the bit manipulation can easily be performed by changing sequentially address and bit specification, it is convenient when processing data comprising a large number of bits bit-wise. fig. 5-7 bit sequential buffer format remarks in pmem. @l addressing, the specified bit moves according to the l register. 321032 1 0 32103210 l = 0 l = 3 l = 4 decs l l = 7 l = 8 incs l l = b l = c l = f fc3h fc2h fc1h fc0h symbol address l register bsb3 bsb2 bsb1 bsb0 bit
27 m pd75108f,75112f,75116f 6. interrupt function the m pd75116f has 7 interrupt sources. multiple interrupts with priority is are also possible. two test sources are also provided. the test sources are edge detection testable inputs. table 6-1 interrupt sources intbt (standard time interval signal from basic interval timer) int4 (both rising edge and falling edge detection) int0 int1 intt0 (match signal from timer/event counter# 0 or ti0 input edge detection) intt1 (match signal from timer/event counter# 1 or ti1 input edge detection) int2 *2 (rising edge detection) int3 *2 (rising edge detection) vector interrupt request signal (vector table address) (rising edge and falling edge detection selection) internal external 1 2 interrupt order *1 internal/external interrupt source external external vrq1 (0002h) vrq3 (0006h) intsio (serial data transfer end signal) internal internal/external internal/external 3 4 5 vrq4 (0008h) vrq5 (000ah) vrq2 (0004h) external testable input signal (set irq2 and irq3) *1. the interrupt order is the priority order when multiple interrupt requests are generated simultaneously. 2. int2 and int3 are of test sources . these are affected by interrupt enable flags in the same way as interrupt sources, but do not generate vector interrupts. the m pd75116f interrupt control circuit has the following functions: hardware control vector interrupt function that can control interrupt acceptance by interrupt enable flag (ie ) and interrupt master enable flag (ime). arbitrary setting of interrupt start address. multiple interruption function by which priority can be specified using the interrupt priority selection register (ips). interrupt request flag (irq ) test function (interrupt generation confirmation by software possible). standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).
28 m pd75108f,75112f,75116f fig. 6-1 interrupt control circuit block diagram 22 im1 im0 irqbt int4 /p00 int0 /p10 int1 /p11 int2 /p12 irq4 irq0 irq1 irqsio irqt0 irqt1 irq2 int bt intsio intt0 intt1 (ime) ist internal bus vector table address generator priority control circuit standby release signal interrupt enable flag (ie xxx ) edge detection circuit edge detection circuit decoder ips 42 int3 /p13 edge detection circuit edge detection circuit interrupt request flag 9 irq3 edge detection circuit
29 m pd75108f,75112f,75116f 7. standby function to reduce the power consumption during program wait, the m pd75116f has two standby modes (stop mode and halt mode). table 7-1 standby mode setting and operation status interrupt request signal from operable hardware enabled by interrupt enable flag, or reset input stop mode stop instruction system clock oscillation stopped operation possible only when the external sck input and to0 output (when timer/event counter 0 is external ti0 input) are selected as a serial clock operable only when tin pin input specified as count clock operation stopped operation of int0 to int4 possible operation stopped setting instruction clock generator circuit basic interval timer operation status halt mode halt instruction only cpu clock f stopped operable (irqbt set at reference time intervals) operation possible if a clock other than f is specified as a serial clock except cpu clock f , output possible. operation stopped serial interface timer/event counter clock output circuit external interrupt cpu operation possible release signal operation stopped
30 m pd75108f,75112f,75116f 8. reset function the reset operation timing is shown in fig. 8-1. fig. 8-1 reset operation by reset input the state of hardware after reset operation is as shown in table 8-1. wait (approx. 31.3 ms: 4.19 mhz) halt mode operating mode internal reset operation operating mode or standby mode reset input
31 m pd75108f,75112f,75116f reset input in standby mode table 8-1 status of each hardware after resetting hardware low-order 5 bits of program memory address 0000h are set in pc 12 to pc 8 and the contents of address 0001h are set in pc 7 to pc 0 . low-order 6 bits of program memory address 0000h are set in pc 13 to pc 8 and the contents of address 0001h are set in pc 7 to pc 0 . held 0 0 sets program memory address 0000h bit 6 and bit 7 to rbe and mbe, respectively. undefined held * held 0, 0 undefined 0 0 ffh 0 0, 0 held 0 0 0 reset (0) 0 0 0, 0 off clear (0) 0 undefined 0 0 reset input during operation undefined 0 0 same as left undefined undefined undefined 0, 0 undefined 0 0 ffh 0 0, 0 undefined 0 0 0 reset (0) 0 0 0, 0 off clear (0) 0 undefined 0 0 carry flag (cy) skip flag (sk0 to sk2) interrupt status flag (ist0, ist1) bank enable flag (mbe, rbe) stack pointer (sp) data memory (ram) general register (x, a, h, l, d, e, b, c) bank selection register (mbs, rbs) psw counter (bt) mode register (btm) counter (tn) modulo register (tmodn) mode register (tmn) toen, tofn shift register (sio) mode register (siom) processor clock control register (pcc) clock output mode register (clom) interrupt request flag (irq ) interrupt enable flag (ie ) priority selection register (ips) int0, 1 mode registers (im0, im1) output buffer output latch i/o mode register (pmga, b, c) pth00 to 03 input latch mode register (pthm) bit sequential buffer (bsb0 to bsb3) basic interval timer timer/event counter (n = 0, 1) serial interface clock generator, clock output circuit interrupt digital port analog port m pd75108f m pd75112f m pd75116f * data of data memory addresses 0f8h to 0fdh becomes undefined by reset input. same as left program counter (pc)
32 m pd75108f,75112f,75116f identifier description reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hl-, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label * bit 2-bit immediate data or label fmem fb0h to fbfh, ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label m pd75108f 0000h to 1f7fh immediate data or label addr m pd75112f 0000h to 2f7fh immediate data or label m pd75116f 0000h to 3f7fh immediate data or lebel caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (however, bit0 = 0) or label portn port 0 to port 9, port12 to port14 ie iebt, iesio, iet0, iet1, ie0 to ie4 rbn rb0 to rb3 mbn mb0, mb1, mb15 9. instruction set (1) operand identifier and description the operand is described in the operand field of each instruction in accordance with the description for the operand identifier of the instruction. (for details, refer to ra75x assembler package users manual language volume (eeu-730) .) when there are multiple elements in the description, one of the elements is selected. upper case letters and symbols (+,C) are keywords and are described unchanged. various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (for details, refer to m pd75116 users manual (iem-922) .) however, there are restrictions on the labels for which fmem and pmem can be used. * in the case of the 8-bit data processing, an even address only can be described for mem.
33 m pd75108f,75112f,75116f (2) operation description legend a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa' : extension register pair (xa') bc' : extension register pair (bc') de' : extension register pair (de') hl' : extension register pair (hl') pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : portn (n = 0 to 9, 12 to 14) ime : interrupt master enable flag ips : interrupt priority selection register ie : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : address, bit delimiter ( ) : contents addressed by h : hexadecimal data
34 m pd75108f,75112f,75116f (3) description of addressing area field symbols *1 *2 data memory addressing *3 *4 *5 *6 mb = mbe ? mbs (mbs = 0, 1, 15) mb = 0 mbe = 0 : mb = 0 (00h to 7fh) mb = 15 (80h to ffh) mbe = 1 : mb = mbs (mbs = 0, 1, 15) mb = 15, fmem = fb0h to fbfh, ff0h to fffh mb = 15, pmem = fc0h to fffh m pd75108f : addr = 0000h to 1f7fh m pd75112f : addr = 0000h to 2f7fh m pd75116f : addr = 0000h to 3f7fh addr = (current pc) C15 to (current pc) + 16 m pd75108f : caddr = 0000h to 0fffh (pc 12 = 0) or = 1000h to 1f7fh (pc 12 = 1) m pd75112f : caddr = 0000h to 0fffh (pc 13 , pc 12 = 00b) or = 1000h to 1fffh (pc 13 , pc 12 = 01b) or = 2000h to 2f7fh (pc 13 , pc 12 = 10b) m pd75116f : caddr = 0000h to 0fffh (pc 13 , pc 12 = 00b) or = 1000h to 1fffh (pc 13 , pc 12 = 01b) or = 2000h to 2fffh (pc 13 , pc 12 = 10b) or = 3000h to 3f7fh (pc 13 , pc 12 = 11b) faddr = 0000h to 07ffh taddr = 0020h to 007fh *7 *8 *9 *10 program memory addressing remarks 1. mb indicates the accessible memory bank. 2. for *2, mb = 0 without regard to mbe and mbs. 3. for *4 and *5, mb = 15 without regard to mbe and mbs. 4. *6 to *10 indicate the addressable area. (4) explanation of machine cycle field s shows the number of machine cycles required when skip is performed by an instruction with skip. the value of s changes as follows: ? no skip ....................................................................................................................................................................... s = 0 ? when instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... s = 1 ? when instruction to be skipped is 3-byte instruction (br !addr, call !addr instructions) ........................... s = 2 note one machine cycle is required to skip a geti instruction. one machine cycle is equivalent to one cycle (= t cy ) of the cpu clock f . three times can be selected by pcc setting.
35 m pd75108f,75112f,75116f a, #n4 reg1, #n4 xa, #n8 hl, #n8 rp2, #n8 a, @hl a, @hl+ a, @hl- a, @rpa1 xa, @hl @hl, a @hl, xa a, mem xa, mem mem, a mem, xa a, reg xa, rp' reg1, a rp'1, xa a, @hl a, @hl+ a, @hl- a, @rpa1 xa, @hl a, mem xa, mem a,reg1 xa, rp' xa, @pcde xa, @pcxa 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 2 2 2 2 1 2 + s 2 + s 1 2 1 2 2 2 2 2 2 2 2 2 1 2 + s 2 + s 1 2 2 2 1 2 3 3 a ? n4 reg1 ? n4 xa ? n8 hl ? n8 rp2 ? n8 a ? (hl) a ? (hl), then l ? l + 1 a ? (hl), then l ? l C 1 a ? (rpa1) xa ? (hl) (hl) ? a (hl) ? xa a ? (mem) xa ? (mem) (mem) ? a (mem) ? xa a ? reg xa ? rp' reg1 ? a rp'1 ? xa a ? (hl) a ? (hl), then l ? l + 1 a ? (hl), then l ? l C 1 a ? (rpa1) xa ? (hl) a ? (mem) xa ? (mem) a ? reg1 xa ? rp' ? m pd75108f xa ? (pc 12-8 + de) rom ? m pd75112f, 75116f xa ? (pc 13-8 + de) rom ? m pd75108f xa ? (pc 12-8 + xa) rom ? m pd75112f, 75116f xa ? (pc 13-8 + xa) rom skip condition stack a stack a stack b l = 0 l = fh l = 0 l = fh *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *1 *1 *2 *1 *3 *3 transfer table reference mnemonic operands bytes machine cycles operation instruction group movt addressing area xch mov
36 m pd75108f,75112f,75116f cy, fmem.bit cy, pmem.@l cy, @h+mem.bit fmem.bit, cy pmem.@l, cy @h+mem.bit, cy a, #n4 xa, #n8 a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa cy ? (fmem.bit) cy ? (pmem 7 C 2 + l 3 C 2 .bit(l 1C0 )) cy ? (h + mem 3 C 0 .bit) (fmem.bit) ? cy (pmem 7 C 2 + l 3 C 2 .bit(l 1C0 )) ? cy (h + mem 3 C 0 .bit) ? cy a ? a + n4 xa ? xa + n8 a ? a + (hl) xa ? xa + rp' rp'1 ? rp'1 + xa a, cy ? a + (hl) + cy xa, cy ? xa + rp' + cy rp'1, cy ? rp'1 + xa + cy a ? a C (hl) xa ? xa C rp' rp'1 ? rp'1 C xa a, cy ? a C (hl) C cy xa, cy ? xa C rp' C cy rp'1, cy ? rp'1 C xa C cy a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa skip condition operands bytes machine cycles operation addressing area *4 *5 *1 *4 *5 *1 *1 *1 *1 *1 *1 *1 *1 carry carry carry carry carry borrow borrow borrow instruction group mnemonic mov1 bit transfer adds 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 addc subc and operations 2 2 2 2 2 2 1 + s 2 + s 1 + s 2 + s 2 + s 1 2 2 1 + s 2 + s 2 + s 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 subs or xor
37 m pd75108f,75112f,75116f a a reg rp1 @hl mem reg rp' reg, #n4 @hl, #n4 a, @hl xa, @hl a, reg xa, rp' cy cy cy cy mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit fmem.bit pmem.@l @h + mem.bit operands operation instruction group mne- monic bytes 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 machine cycles cy a 0 , a 3 cy, a nC1 a n a a reg reg + 1 rp1 rp1 + 1 (hl) (hl) + 1 (mem) (mem) + 1 reg reg C 1 rp' rp' C 1 skip if reg = n4 skip if (hl) = n4 skip if a = (hl) skip if xa = (hl) skip if a = reg skip if xa = rp' cy 1 cy 0 skip if cy = 1 cy cy (mem.bit) 1 (fmem.bit) 1 (pmem 7C2 + l 3C2 .bit (l 1C0 )) 1 (h + mem 3C0 .bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem 7C2 + l 3C2 .bit (l 1C0 )) 0 (h + mem 3C0 .bit) 0 skip if (mem.bit) = 1 skip if (fmem.bit) = 1 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 skip if (h + mem 3C0 .bit) = 1 skip if (mem.bit) = 0 skip if (fmem.bit) = 0 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 0 skip if (h + mem 3C0 .bit) = 0 skip if (fmem.bit) = 1 and clear skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 and clear skip if (h + mem 3C0 .bit) = 1 and clear addressing area skip condition reg = 0 rp1 = 00h (hl) = 0 (mem) = 0 reg = fh rp' = ffh reg = n4 (hl) = n4 a = (hl) xa = (hl) a = reg xa = rp' cy = 1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@l) = 0 (@h + mem.bit) = 0 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 1 2 1 + s 1 + s 2 + s 2 + s 1 + s 2 + s 2 + s 2 + s 1 + s 2 + s 2 + s 2 + s 1 1 1 + s 1 2 2 2 2 2 2 2 2 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s rorc *1 *3 *1 *1 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 accumulator manipulation not incs increment /decrement decs ske comparison set1 clr1 skt not1 carry flag manipulation set1 memory bit manipulation clr1 skt skf sktclr
38 m pd75108f,75112f,75116f cy ? cy (fmem.bit) cy ? cy (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? cy (h + mem 3C0 .bit) cy ? cy (fmem.bit) cy ? cy (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? cy (h + mem 3C0 .bit) cy ? cy (fmem.bit) cy ? cy (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? cy (h + mem 3C0 .bit) ? m pd75108f pc 12C0 ? addr (the assembler selects the optimum in- struction from among the br !addr, brcb !caddr, and br $addr instructions.) ? m pd75112f, 75116f pc 13C0 ? addr (the assembler selects the optimum in- struction from among the br !addr, brcb !caddr, and br $addr instructions.) ? m pd75108f pc 12-0 ? addr ? m pd75112f, 75116f pc 13-0 ? addr ? m pd75108f pc 12-0 ? addr ? m pd75112f, 75116f pc 13-0 ? addr ? m pd75108f pc 12-0 ? pc 12 + caddr 11-0 ? m pd75112f, 75116f pc 13-0 ? pc 13 , pc 12 + caddr 11-0 ? m pd75108f pc 12-0 ? pc 12-8 + de ? m pd75112f, 75116f pc 13-0 ? pc 13-8 + de ? m pd75108f pc 12-0 ? pc 12-8 + xa ? m pd75112f, 75116f pc 13-0 ? pc 13-8 + xa ? m pd75108f (sp-4) (sp-1) (sp-2) ? pc 11-0 (sp-3) ? mbe, rbe, 0, pc 12 pc 12-0 ? addr, sp ? spC4 ? m pd75112f, 75116f (sp-4) (sp-1) (sp-2) ? pc 11-0 (sp-3) ? mbe, rbe, pc 13 , pc 12 pc 13-0 ? addr, sp ? spC4 instruction group mne- monic branch cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit addr !addr $addr !caddr pcde pcxa !addr bytes machine cycles addressing area skip condition operation operands *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 *6 *7 *8 *6 and1 memory bit manipulation xor1 2 2 2 2 2 2 2 2 2 3 2 2 3 3 3 2 2 2 2 2 2 2 2 2 3 1 2 2 2 3 subroutine stack control or1 br brcb br call
39 m pd75108f,75112f,75116f ? m pd75108f (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, rbe, 0, pc 12 pc 12C0 ? 00, faddr, sp ? sp C 4 ? m pd75112f, 75116f (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, rbe, pc 13 , pc 12 pc 13C0 ? 000, faddr, sp ? sp C 4 ? m pd75108f mbe, rbe, , pc 12 ? (sp + 1) pc 11C0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 ? m pd75112f, 75116f mbe, rbe, pc 13 , pc 12 ? (sp + 1) pc 11C0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4 ? m pd75108f mbe, rbe, , pc 12 ? (sp + 1) pc 11C0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4, then skip unconditionally ? m pd75112f, 75116f mbe, rbe, pc 13 , pc 12 ? (sp + 1) pc 11C0 ? (sp) (sp + 3) (sp + 2) sp ? sp + 4, then skip unconditionally ? m pd75108f mbe, rbe, , pc 12 ? (sp + 1) pc 11C0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5 ), sp ? sp + 6 ? m pd75112f, 75116f mbe, rbe, pc 13 , pc 12 ? (sp + 1) pc 11C0 ? (sp) (sp + 3) (sp + 2) psw ? (sp + 4) (sp + 5 ), sp ? sp + 6 (sp C 1) (sp C 2) ? rp, sp ? sp C 2 (sp C 1) ? mbs, (sp C 2) ? rbs, sp ? sp C 2 rp ? (sp + 1) (sp), sp ? sp + 2 mbs ? (sp + 1), rbs ? (sp), sp ? sp + 2 ime (ips.3) ? 1 ie ? 1 ime (ips.3) ? 0 ie ? 0 operation instruction group mne- monic skip condition operands bytes machine cycles addressing area *9 2 2 !faddr 3 1 callf ret 3 + s 1 rets subroutine stack control reti 3 1 push pop ei di rp bs rp bs ie ie 1 2 1 2 2 2 2 2 1 2 1 2 2 2 2 2 unconditional interrupt control
40 m pd75108f,75112f,75116f operation instruction group mne- monic skip condition operands addressing area ------------------------ bytes machine cycles 2 2 2 2 2 2 1 2 2 2 2 2 2 2 2 1 2 2 a ? portn (n = 0 to 9, 12 to 14) xa ? portn + 1 , portn (n = 4, 6, 8, 12) portn ? a (n = 2 to 9, 12 to 14) portn + 1 , portn ? xa (n = 4, 6, 8, 12) set halt mode (pcc.2 ? 1) set stop mode (pcc.3 ? 1) no operation rbs ? n (n = 0 to 3) mbs ? n (n = 0, 1, 15) ? m pd75108f tbr instruction pc 12C0 ? (taddr) 4C0 ? (taddr + 1) tcall instruction (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, rbe, 0, pc 12 pc 12C0 ? (taddr) 4C0 ? (taddr + 1) sp ? sp C 4 other than tbr and tcall instruction execution of an instruction addressed at (taddr) and (taddr + 1) ? m pd75112f, 75116f tbr instruction pc 13C0 ? (taddr) 5C0 ? (taddr + 1) tcall instruction (sp C 4) (sp C 1) (sp C 2) ? pc 11C0 (sp C 3) ? mbe, rbe, 0, pc 13 , pc 12 pc 13C0 ? (taddr) 5C0 ? (taddr + 1) sp ? sp C 4 other than tbr and tcall instruction execution of an instruction addressed at (taddr) and (taddr + 1) a, portn xa, portn portn, a portn, xa rbn mbn *1 halt stop nop in *1 out input/output cpu control sell ---------------------------------------------------------- ---------------------------------------------------------- *10 ---------------------------------------------------------- 3 1 taddr *2 geti special ---------------------------------------------------------- ----------------------- conforms to referenced instruction. conforms to referenced instruction. *1. when executing the in/out instruction, or must be set. 2. the tbr or tcall instruction is a geti instruction table definition assembler pseudo-instruction.
41 m pd75108f,75112f,75116f power amp idc amp compres- sion transmitter/ receiver extension mpx msk modem speaker speaker amp led display key matrix led display lcd controller/ driver console detection id rom sio radio wave detection extra-area detection tcxo pll vco prescaler pll vco prescaler mpx mixer 2sc4226 1ss281 3sk177 filter amp 2sc2757 2sc4182 10. application example 10.1 cordless telephone (subset) legend idc : immediate deviation controller, id rom : id (identification) code rom, lcd : liquid crystal display, led : light emitting diode, mpx : multiplexer, msk : minimum shift keying, pll : phase locked loop, sio : serial data input/output, tcxo : temperature compensation crystal oscillator, vco : voltage control oscillator m pd2840 m pd2841 m pd6130 m pd6131 m pd6252 m pd7228 m pd75116f
42 m pd75108f,75112f,75116f filter int to code rom piezoelectric buzzer comparator input high-current output led display switch ram pd446 battery check lcd display lcd controller/driver pd7228/7229 sio pd75116f m m m 10.2 display pager
43 m pd75108f,75112f,75116f 11. mask option selection the m pd75116f has the following mask option to select whether or not a pull-up resistor is incorporated. pin mask option p120 to p123 p130 to p133 pull-up resistor can be incorporated bit-wise. p140 to p143
44 m pd75108f,75112f,75116f 12. electrical specifications absolute maximum ratings (ta = 25 c) parameter symbol test conditions rating unit except ports 12, 13 and 14 C0.3 to v dd +0.3 v input voltage internal pull-up resistor C0.3 to v dd +0.3 v ports 12 to 14 openCdrain C0.3 to +11 v output voltage C0.3 to v dd +0.3 v one pin C15 ma all pins C30 ma peak value 30 ma one pin effective value 15 ma peak value 100 ma output current low effective value 60 ma peak value 100 ma total of ports 5 to 9 effective value 60 ma operating temperature storage temperature *1. when a voltage exceeding 10v is applied to ports 12, 13 and 14, the power supply impedance (pull-up resistor) should be 50k w or more. 2. effective value should be calculated: [effective value] = [peak value] ? duty note product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. supply voltage C0.3 to +5.5 v v i1 v i2 *1 v o i oh i ol *2 t opt t stg v dd C40 to +60 c C65 to +150 c output current high total of ports 0, 2 to 4, 12 to 14
45 m pd75108f,75112f,75116f 12.1 when ta = C40 to +50 c, v dd = 2.7 to 5.0 v operating voltage (ta = C40 to +50 c) cpu *1 programmable threshold port (comparator input) other hardware *1 *2 5.0 v 4.5 5.0 v 2.7 5.0 v parameter test conditions min. max. unit *1. except system clock oscillation circuit, programmable threshold port. 2. the operable supply voltage range depends on the cycle time. see "ac characteristics". oscillation circuit characteristics (ta = C40 to +50 c, v dd = 2.7 to 5.0 v) recommended test resonator parameter min. typ. max. unit constant conditions ceramic resonator after v dd reaches min. of oscillation voltage range crystal resonator external clock 2.0 5.0 *3 mhz 4ms 2.0 4.19 5.0 *3 mhz v dd = 4.5 to 5.0 v 10 ms 30 ms 2.0 5.0 *3 mhz 100 250 ns oscillator frequency (f xx ) *1 oscillation stabilization time *2 oscillator frequency (f xx ) *1 oscillation stabilization time *2 x1 input frequency (f x ) *1 x1 input high-/low-level width (t xh , t xl ) x1 x2 m pd74hcu04 v dd = oscillation voltage range x1 x2 c1 c2 x1 x2 c1 c2 *1. oscillator frequency and x1 input frequency indicate oscillation circuit characteristics only. see ac characteristics for instruction execution time. 2. the oscillation stabilization time is the time required for oscillation to stabilize after v dd reaches min. of oscillation voltage range or the stop mode is released. 3. when the oscillator frequency is 4.19 mhz < f xx 5.0 mhz, pcc = 0011 should not be selected as the instruction execution time. if pcc = 0011 is selected, one machine cycle is less than 0.95 m s and the rated min. value of 0.95 m s is not observed. note when the clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. the wiring should be kept as short as possible. no other signal lines should be crossed. keep away from lines carrying a high fluctuating current. the oscillator capacitor grounding point should always be at the same potential as v ss . do not connect to a ground pattern carrying a high current. a signal should be not taken from the oscillator. h
46 m pd75108f,75112f,75116f recommended oscillation circuit constant recommended ceramic resonator (ta = C40 to +50 c) product name csa 2.00mg csa 4.19mg csa 4.19mgu cst 4.19t kbrC2.0ms kbrC4.0ms kbrC4.19ms kbrC4.9152m c1 30 30 30 CC 100 33 33 33 c2 30 30 30 CC 100 33 33 33 manufacturer murata mfg. kyocera external capacitance [pf] min. 2.7 3.0 2.7 3.0 3.0 3.0 3.0 3.0 max. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 oscillation voltage range [v] recommended crystal resonator (ta = C20 to +50 c) product name hc-49/u c1 22 c2 22 manufacturer external capacitance [pf] min. 2.7 max. 5.0 oscillation voltage range [v] kinseki
47 m pd75108f,75112f,75116f other than below ports 0,1,ti0, 1, reset internal pull-up resistor ports 12 and 14 openCdrain x1, x2 other than below ports 0,1,ti0, 1, reset x1, x2 v dd = 4.5 to 5.0 v, i oh = C1 ma i oh = C100 m a ports 0, 2 to 9, i ol = 15 ma v dd = 4.5 to 5.0 v ports 12 to 14, i ol = 10 ma v dd = 4.5 to 5.0 v, i ol = 1.6 ma i ol = 400 m a other than below v in = v dd x1, x2 v iv = 10 v ports 12 to 14 (open-drain) except x1, x2 v in = 0 v x1, x2 v out = v dd other than below v out = 10 v ports 12 to 14 (open-drain) v dd = 4.5 to 5.0 v ports 12 to 14 v dd = 4.5 to 5.0 v *2 v dd = 3 v 10 % *3 v dd = 4.5 to 5.0 v v dd = 3 v 10 % stop mode, v dd = 3 v 10 % dc characteristics (ta = C40 to +50 c, v dd = 2.7 to 5.0 v) parameter symbol test conditions min. typ. max. unit v ih1 v ih2 v ih3 v ih4 input voltage high v il1 v il2 v il3 input voltage low v oh output voltage high v ol output voltage low i lih1 i lih2 i lih3 input leakage current high input leakage current low i lil1 i lil2 i loh1 i loh2 output leakage current high output leakage current low v out = 0 v i lol internal pull-up resistor (mask option) r l i dd1 4.19 mhz crystal oscillation c1 = c2 = 22 pf halt mode i dd2 i dd3 supply current *1 C3 m a *1. excluding current flowing in the internal pull-up resistors and comparator circuit. 2. when the processor clock control register (pcc) is set to 0011 for operation in the high-speed mode. 3. when the pcc register is set to 0000 for operation in the low-speed mode. 0.7 v dd v dd v 0.8 v dd v dd v 0.7 v dd v dd v 0.7 v dd 12 v v dd C 0.5 v dd v 0 0.3 v dd v 0 0.2 v dd v 0 0.4 v v dd C 1.0 v v dd C 0.5 v 0.35 2.0 v 0.35 2.0 v 0.4 v 0.5 v 3 m a 20 m a 20 m a C3 m a C20 m a 3 m a 20 m a 15 40 70 k w 10 80 k w 39ma 0.55 1.5 ma 600 1800 m a 200 600 m a 0.1 10 m a
48 m pd75108f,75112f,75116f 100 mv 0v dd v 0v dd v capacitance (ta = 25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit c in c out 15 pf 15 pf input capacitance output capacitance input/output capacitance c io f = 1 mhz unmeasured pins returned to 0 v 15 pf comparator characteristics (ta = C40 to +50 c, v dd = 4.5 to 5.0 v) parameter symbol test conditions min. typ. max. unit v acomp v th v ipth compare accuracy threshold voltage pth input voltage comparator circuit current consump- tion pthm7 set to "1" 1ma
49 m pd75108f,75112f,75116f 0.95 32 m s 1.91 32 m s 0 1 mhz 0 275 khz 0.48 m s 1.8 m s 0.8 m s 0.95 m s 3.2 m s 3.8 m s 0.4 m s t kcy /2 C 50 ns 1.6 m s t kcy /2 C 150 ns 300 ns 1000 ns v dd = 4.5 to 5.0 v v dd = 4.5 to 5.0 v v dd = 4.5 to 5.0 v input v dd = 4.5 to 5.0 v output input output input v dd = 4.5 to 5.0 v output input output v dd = 4.5 to 5.0 v ac characteristics (ta = C40 to +50 c, v dd = 2.7 to 5.0 v) parameter symbol test conditions min. typ. max. unit f ti t tih , t til t cy t ksi t sik t kso 100 ns 400 ns ti0, ti1 input frequency ti0, ti1 input high/ low-level width t kcy sck cycle time sck high/low-level width t kh , t kl si setup time (to sck - ) si hold time (from sck - ) so output delay time from sck int0 to int4 high/low-level width reset low-level width t inth , t intl t rsl 5 m s 5 m s cpu clock cycle time * (minimum instruction execution time = 1 machine cycle)
50 m pd75108f,75112f,75116f t cy vs. v dd t cy [ s] v dd [v] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 7 32 40 6 m operating guarantee range * the cpu clock f cycle time is determined by the oscillation frequency of the connected resonator and the setting of the processor clock control register (pcc). the graph on the right shows the characteristic for cycle time t cy supply current v dd during system clock operation.
51 m pd75108f,75112f,75116f ac timing test point (except ports 0, 1, ti0, ti1, x1, x2, reset) clock timing ti0,ti1 input timing x1 input 1/f x t xl t xh v dd ?0.5 v 0.4 v ti0, ti1 1/f ti t til t tih 0.8 v dd 0.2 v dd 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd test points
52 m pd75108f,75112f,75116f serial transfer timing interrupt input timing t intl t inth int0?nt4 0.8 v dd 0.2 v dd reset input timing t rsl reset 0.2 v dd sck input data output data t kso si so 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t kcy t kh t kl t sik t ksi
53 m pd75108f,75112f,75116f wait time btm3 btm2 btm1 btm0 (figures in parentheses are for operation at f xx = 4.19 mhz) 0 00 2 20 /f xx (approx. 250 ms) 0 11 2 17 /f xx (approx. 31.3 ms) 1 01 2 15 /f xx (approx. 7.82 ms) 1 11 2 13 /f xx (approx. 1.95 ms) data retention timing (stop mode release by reset) *1. excluding current flowing in the internal pull-up resistors and comparator circuit. 2. the oscillation stabilization wait time is the time during which cpu operation is stopped to prevent unstable operation when oscillation is started. 3. depends on the basic interval timer mode register (btm) setting (see table below). data memory stop mode low supply voltage data retention characteristics (ta = C40 to +50 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 2.0 5.0 v data retention supply current *1 i dddr v dddr = 2.0 v 0.1 10 m a release signal set time t srel 0 m s release by reset 2 17 /f xx ms oscillation stabilization time *2 t wait release by interrupt request *3 ms stop mode data retention mode stop instruction execution reset v dd internal reset operation halt mode operating mode v dddr t srel t wait
54 m pd75108f,75112f,75116f data retention timing (standby release signal: stop mode release by interrupt signal) stop mode data retention mode stop instruction execution v dd halt mode operating mode v dddr t srel t wait standby release signal (interrupt request)
55 m pd75108f,75112f,75116f 12.2 when ta = C40 to +60 c, v dd = 2.8 to 5.0 v operating voltage (ta = C40 to +60 c) cpu *1 programmable threshold port (comparator input) other hardware *1 *2 5.0 v 4.5 5.0 v 2.8 5.0 v parameter test conditions min. max. unit *1. except system clock oscillation circuit, programmable threshold port. 2. the operable supply voltage range depends on the cycle time. see "ac characteristics". oscillation circuit characteristics (ta = C40 to +60 c, v dd = 2.8 to 5.0 v) recommended test resonator parameter min. typ. max. unit constant conditions ceramic resonator after v dd reaches min. of oscillation voltage range crystal resonator external clock 2.0 5.0 *3 mhz 4ms 2.0 4.19 5.0 *3 mhz v dd = 4.5 to 5.0 v 10 ms 30 ms 2.0 5.0 *3 mhz 100 250 ns oscillator frequency (f xx ) *1 oscillation stabilization time *2 oscillator frequency (f xx ) *1 oscillation stabilization time *2 x1 input frequency (f x ) *1 x1 input high-/low-level width (t xh , t xl ) x1 x2 m pd74hcu04 v dd = oscillation voltage range x1 x2 c1 c2 x1 x2 c1 c2 *1. oscillator frequency and x1 input frequency indicate oscillation circuit characteristics only. see ac characteristics for instruction execution time. 2. the oscillation stabilization time is the time required for oscillation to stabilize after v dd reaches min. of oscillation voltage range, or the stop mode is released. 3. when the oscillator frequency is 4.19 mhz < f xx 5.0 mhz, pcc = 0011 should not be selected as the instruction execution time. if pcc = 0011 is selected, one machine cycle is less than 0.95 m s and the rated min. value of 0.95 m s is not observed. note when the clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. the wiring should be kept as short as possible. no other signal lines should be crossed. keep away from lines carrying a high fluctuating current. the oscillator capacitor grounding point should always be at the same potential as v ss . do not connect to a ground pattern carrying a high current. a signal should be not taken from the oscillator. h
56 m pd75108f,75112f,75116f recommended oscillation circuit constant recommended ceramic resonator (ta = C40 to +60 c) product name csa 2.00mg csa 4.19mg csa 4.19mgu cst 4.19t kbrC2.0ms kbrC4.0ms kbrC4.19ms kbrC4.9152m c1 30 30 30 CC 100 33 33 33 c2 30 30 30 CC 100 33 33 33 manufacturer murata mfg. kyocera external capacitance [pf] min. 2.7 3.0 2.7 3.0 3.0 3.0 3.0 3.0 max. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 oscillation voltage range [v] recommended crystal resonator (ta = C20 to +60 c) product name hc-49/u c1 22 c2 22 manufacturer external capacitance [pf] min. 2.7 max. 5.0 oscillation voltage range [v] kinseki
57 m pd75108f,75112f,75116f other than below ports 0,1,ti0, 1, reset internal pull-up resistor ports 12 to 14 openCdrain x1, x2 other than below ports 0,1,ti0, 1, reset x1, x2 v dd = 4.5 to 5.0 v, i oh = C1 ma i oh = C100 m a ports 0, 2 to 9, i ol = 15 ma v dd = 4.5 to 5.0 v ports 12 to 14, i ol = 10 ma v dd = 4.5 to 5.0 v, i ol = 1.6 ma i ol = 400 m a other than below v in = v dd x1, x2 v iv = 10 v ports 12 to 14 (open-drain) except x1, x2 v in = 0 v x1, x2 v out = v dd other than below v out = 10 v ports 12 to 14 (open-drain) v dd = 4.5 to 5.0 v ports 12 to 14 v dd = 4.5 to 5.0 v *2 v dd = 2.8 to 3.3 v *3 v dd = 4.5 to 5.0 v v dd = 2.8 to 3.3 v stop mode, v dd = 2.8 to 3.3 v dc characteristics (ta = C40 to +60 c, v dd = 2.8 to 5.0 v) parameter symbol test conditions min. typ. max. unit v ih1 v ih2 v ih3 v ih4 input voltage high v il1 v il2 v il3 input voltage low v oh output voltage high v ol output voltage low i lih1 i lih2 i lih3 input leakage current high input leakage current low i lil1 i lil2 i loh1 i loh2 output leakage current high output leakage current low v out = 0 v i lol internal pull-up resistor (mask option) r l i dd1 4.19 mhz crystal oscillation c1 = c2 = 22 pf halt mode i dd2 i dd3 supply current *1 C3 m a *1. excluding current flowing in the internal pull-up resistors and comparator circuit. 2. when the processor clock control register (pcc) is set to 0011 for operation in the high-speed mode. 3. when the pcc register is set to 0000 for operation in the low-speed mode. 0.7 v dd v dd v 0.8 v dd v dd v 0.7 v dd v dd v 0.7 v dd 10 v v dd C 0.5 v dd v 0 0.3 v dd v 0 0.2 v dd v 0 0.4 v v dd C 1.0 v v dd C 0.5 v 0.35 2.0 v 0.35 2.0 v 0.4 v 0.5 v 3 m a 20 m a 20 m a C3 m a C20 m a 3 m a 20 m a 15 40 70 k w 10 80 k w 39ma 0.55 1.5 ma 600 1800 m a 200 600 m a 0.1 10 m a
58 m pd75108f,75112f,75116f 100 mv 0v dd v 0v dd v capacitance (ta = 25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit c in c out 15 pf 15 pf input capacitance output capacitance input/output capacitance c io f = 1 mhz unmeasured pins returned to 0 v 15 pf comparator characteristics (ta = C40 to +60 c, v dd = 4.5 to 5.0 v) parameter symbol test conditions min. typ. max. unit v acomp v th v ipth compare accuracy threshold voltage pth input voltage comparator circuit current consump- tion pthm7 set to "1" 1ma
59 m pd75108f,75112f,75116f 0.95 32 m s 1.91 32 m s 0 1 mhz 0 275 khz 0.48 m s 1.8 m s 0.8 m s 0.95 m s 3.2 m s 3.8 m s 0.4 m s t kcy /2 C 50 ns 1.6 m s t kcy /2 C 150 ns 300 ns 1000 ns v dd = 4.5 to 5.0 v v dd = 4.5 to 5.0 v v dd = 4.5 to 5.0 v input v dd = 4.5 to 5.0 v output input output input v dd = 4.5 to 5.0 v output input output v dd = 4.5 to 5.0 v ac characteristics (ta = C40 to +60 c, v dd = 2.8 to 5.0 v) parameter symbol test conditions min. typ. max. unit f ti t tih , t til t cy t ksi t sik t kso 100 ns 400 ns ti0, ti1 input frequency ti0, ti1 input high/ low-level width t kcy sck cycle time sck high/low-level width t kh , t kl si setup time (to sck - ) si hold time (from sck - ) so output delay time from sck int0 to int4 high/low-level width reset low-level width t inth , t intl t rsl 5 m s 5 m s cpu clock cycle time * (minimum instruction execution time = 1 machine cycle)
60 m pd75108f,75112f,75116f t cy vs. v dd t cy [ s] v dd [v] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 7 32 40 6 m operating guarantee range * the cpu clock f cycle time is determined by the oscillation frequency of the connected resonator and the setting of the processor clock control register (pcc). the graph on the right shows the characteristic for cycle time t cy supply current v dd during system clock operation.
61 m pd75108f,75112f,75116f ac timing test point (except ports 0, 1, ti0, ti1, x1, x2, reset) clock timing ti0, ti1 input timing x1 input 1/f x t xl t xh v dd ?0.5 v 0.4 v ti0, ti1 1/f ti t til t tih 0.8 v dd 0.2 v dd 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd test points
62 m pd75108f,75112f,75116f serial transfer timing sck input data output data t kso si so 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t kcy t kh t kl t sik t ksi interrupt input timing t intl t inth int0?nt4 0.8 v dd 0.2 v dd reset input timing t rsl reset 0.2 v dd
63 m pd75108f,75112f,75116f wait time btm3 btm2 btm1 btm0 (figures in parentheses are for operation at f xx = 4.19 mhz) 0 00 2 20 /f xx (approx. 250 ms) 0 11 2 17 /f xx (approx. 31.3 ms) 1 01 2 15 /f xx (approx. 7.82 ms) 1 11 2 13 /f xx (approx. 1.95 ms) data retention timing (stop mode release by reset) data memory stop mode low supply voltage data retention characteristics (ta = C40 to +60 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 2.0 5.0 v data retention supply current *1 i dddr v dddr = 2.0 v 0.1 10 m a release signal set time t srel 0 m s release by reset 2 17 /f xx ms oscillation stabilization time *2 t wait release by interrupt request *3 ms *1. excluding current flowing in the internal pull-up resistors and comparator circuit. 2. the oscillation stabilization wait time is the time during which cpu operation is stopped to prevent unstable operation when oscillation is started. 3. depends on the basic interval timer mode register (btm) setting (see table below). stop mode data retention mode stop instruction execution reset v dd internal reset operation halt mode operating mode v dddr t srel t wait
64 m pd75108f,75112f,75116f data retention timing (standby release signal: stop mode release by interrupt signal) stop mode data retention mode stop instruction execution v dd halt mode operating mode v dddr t srel t wait standby release signal (interrupt request)
65 m pd75108f,75112f,75116f 13. characteristic curves (reference) supply current i dd [ m a] i dd vs. v dd (crystal oscillator : 4.19 mhz) (ta = 25 ?) supply voltage v dd [v] 1000 100 10 0 1 2 3 4 5 6 x1 x2 22pf 22pf crystal 4.19 mhz halt mode high-speed mode medium-speed mode low-speed mode
66 m pd75108f,75112f,75116f supply current i dd [ma] supply current i dd [ma] 0 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 values in parentheses indicate pcc set values. i dd vs. f xx characteristic examples (crystal oscillation) (v dd = 5.0 v, ta = 25 ?) f xx [mhz] c 1 x1 x2 c 2 high-speed mode [0011] medium-speed mode [0010] low-speed mode [0000] halt mode [0100] 012345 0 0.5 1.0 1.5 2.0 2.5 3.0 values in parentheses indicate pcc set values. i dd vs. f xx characteristic examples (ceramic oscillation) (v dd = 5.0 v, ta = 25 ?) f xx [mhz] c 1 x1 x2 c 2 high-speed mode [0011] medium-speed mode [0010] low-speed mode [0000] halt mode [0100]
67 m pd75108f,75112f,75116f supply current i dd [ma] m pd74hcu04 0 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 values in parentheses indicate pcc set values. i dd vs. f x characteristic examples (external clock) (v dd = 5.0 v, ta = 25 ?) f x [mhz] x1 x2 high-speed mode [0011] medium-speed mode [0010] low-speed mode [0000] halt mode [0100]
68 m pd75108f,75112f,75116f tin input frequency f ti [khz] tin input frequency f ti [khz] 0 0 f ti vs. v dd characteristic (ta = ?0 to +50 ?) v dd [v] 1 2 3 4 5 6 7 100 50 1000 500 operating guarantee range 0 0 f ti vs. v dd characteristic (ta = ?0 to +60 ?) v dd [v] 1 2 3 4 5 6 7 100 50 1000 500 operating guarantee range
69 m pd75108f,75112f,75116f ports 0, 2 to 9 output current low i ol [ma] ports 12 to 14 output current low i ol [ma] 0 0 v ol vs. i ol (ports 0, 2 to 9) characteristic examples v ol [v] v dd = 5 v v dd = 4 v v dd = 3 v 1 2 3 4 10 20 30 0 0 v ol vs. i ol (ports 12 to 14) characteristic examples v ol [v] v dd = 5 v v dd = 4 v v dd = 3 v 1 2 3 4 10 20 30
70 m pd75108f,75112f,75116f ports 0, 2 to 9 output current high i oh [ma] remarks characteristic curves not marked "guarantee range" indicate reference values. 0 0 v oh vs. i oh (ports 0, 2 to 9) characteristic examples v dd ?v oh [v] v dd = 5 v v dd = 4 v v dd = 3 v 1234 -5 -10 -15
71 m pd75108f,75112f,75116f n a m f b 51 52 32 k l 64 pin plastic qfp (14 20) 64 1 20 19 33 p d c detail of lead end s q 55? g m i h j p64gf-100-3b8,3be,3br-1 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 1.0 0.40 0.10 0.20 20.0 0.2 0.929 0.016 0.039 0.039 0.008 0.039 (t.p.) 0.795 note m n 0.12 0.15 1.8 0.2 1.0 (t.p.) 0.005 0.006 +0.004 ?.003 each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 0.071 0.016 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009 14. package information 64-pin plastic qfp (14 20)
72 m pd75108f,75112f,75116f 64-pin ceramic qfp for es (reference diagram) caution 1. note that the metal cap is connected to pin 26, and is at the v ss (gnd) level. 2. note that the leads on the underside are formed at an angle. 3. cutting of the lead tips is not process-controlled, and therefore there is no stan- dard lead length. 14.2 12.0 64 52 151 32 20 19 33 0.4 1.0 2.25 18.0 0.15 bottom view 20
73 m pd75108f,75112f,75116f 15. recommended soldering conditions the m pd75116f should be soldered and mounted under the conditions recommended in the table below. for details of recommended conditions, refer to the information document "semiconductor device mount technology manual" (iei-1207) . for soldering methods and conditions other than those recommended below, contact our salesman. table 15-1 surface mount type soldering conditions m pd75108fgf- -3be : 64-pin plastic qfp (14 20 mm) m pd75112fgf- -3be : 64-pin plastic qfp (14 20 mm) m pd75116fgf- -3be : 64-pin plastic qfp (14 20 mm) recommended condition symbol soldering method soldering conditions infrared reflow vps package peak temperature : 230 c, duration : 30 sec. max. (at 210 c or avove), number of times : once package peak temperature : 215 c, duration : 40 sec. max. (at 200 c or above), number of times : once solder bath temperature : 260 c max., duration : 10 sec. max., number of times : once, preheating temperature : 120 c max. (package surface temperature) pin part temperature : 300 c max., duration : 3 sec. max. (per device side) ir30-00-1 vp15-00-1 pin part heating pin part heating wave soldering ws60-00-1 note use of more than one soldering method should be avoided (except in the case of pin part heating). notice a version of this product with improved recommended soldering conditions is available. for details (improvements such as infrared reflow peak temperature extension (235 c), number of times: twice, relaxation of time limit, etc.), contact nec sales personnel.
74 m pd75108f,75112f,75116f item 4k/6k/8k/12k/16k 4k/8k 8k/12k/16k (mask rom) (mask rom) (mask rom) 320/320/512/512/512 320/512 512 rom (byte) ram ( 4 bits) m pd75104/106/108/112/116 m pd75104a/108a m pd75108f/112f/116f product name appendix a. functional differences among m pd751 series products 10 (pull-up resistor mask option : 4) 32 (pull-up resistor mask option : 24, led direct drive capability) 10 32 (led direct drive capability) 32 (led direct drive capability) 10 withstand voltage cmos input/output n-ch open-drain input/output cmos input total 12 (led direct drive capability) +12 v +10 v instruction set 75x high-end 58 analog input power-on reset circuit power-on flag on-chip (mask option) none 2.7 to 6.0 v C40 to +85 c C40 to +60 c pull-up resistor can be incorporated by mask option 4 (4-bit precision) operating temperature range 2.7 to 5.0 v (ta = C40 to +50 c) 2.8 to 5.0 v minimum instruction execution time 0.95 m s (operating at 4.5 to 6.0 v) 0.95 m s (operating at 4.5 to 5.0 v) 3.8 m s (operating at 2.7 v) 1.91 m s (operating at 2.7v) i/o port package *2 *1. 75x high-end can also be used by means of the 16k-byte mode/24k-byte mode switching function. 2. the following five types of plastic qfp are available. ? g-1b ........ 14 20 2.05 mm, 1.0 mm pitch ? gc-ab8 ... 14 14 2.55 mm, 0.8 mm pitch ? gf-3be .... 14 20 2.7 mm, 1.0 mm pitch ? g-22 ........ 14 14 1.5 mm, 0.8 mm pitch ? gk-7et ... 12 12 1.45 mm, 0.65 mm pitch 3. under development. operating voltage ? 64-pin plastic shrink dip ? 64-pin plastic qfp(gf-3be) ? 64-pin plastic qfp (g-1b) : m pd75104/106/108 only ? 64-pin plastic qfp(gc-ab8) ? 64-pin plastic qfp (g-22) : m pd75108a only ? 64-pin plastic qfp(gf-3be) h
75 m pd75108f,75112f,75116f 16k/24k 8k 24k (mask rom) (one-time prom) (one-time prom) 768 512 768 75x high-end/extended 75x high-end 75x extended high-end high-end *1 58 10 m pd75116h/117h m pd75p108b m pd75p116 m pd75p117h 32 (led direct drive capability : 8) 32 (led direct drive capability) 32 (led direct drive capability : 8) 12 12 (led direct drive capability) 12 +6 v +12 v +6 v can be incorporated by mask option none 4 (4-bit precision) none none 1.8 to 5.0 v C40 to +60 c C40 to +85 c 2.7 to 6.0 v 5 v 10 % 1.8 to 5.0 v C40 to +60 c 0.95 m s (operating at 2.7 v) 1.91 m s (operating at 1.8 v) 0.95 m s (operating at 4.5 to 6.0 v) 3.8 m s (operating at 2.7 v) 0.95 m s (operating at 4.75 to 5.5 v) 0.95 m s (operating at 2.7 v) 1.91 m s (operating at 1.8 v) ? 64-pin plastic qfp (gc-ab8) ? 64-pin plastic qfp (gk-7et) ? 64-pin plastic shrink dip ? 64-pin plastic qfp (gf-3be) ? 64-pin plastic shrink dip ? 64-pin plastic qfp (gf-3be) ? 64-pin ceramic shrink dip with window ? 64-pin plastic qfp (gc-ab8) ? 64-pin plastic qfp (gk-7et) *3
76 m pd75108f,75112f,75116f appendix b. development tools the following development tools are available for system development using the m pd75116f. *1. maintenance product 2. not incorporated in the ie-75001-r. 3. a task swapping function is provided in ver. 5.00/5.00a, but this function cannot be used with this software. remarks please refer to the 75x series selection guide (if-151) for third party development tools. h ie-75000-r *1 ie-75001-r ie-75000-r-em*2 ep-75108gf-r pg-1500 pa-75p116gf ie control program pg-1500 controller ra75x relocatable assembler 75x series in-circuit emulator emulation board for the ie-75000-r or ie-75001-r emulation probe for the m pd75116fgf. a 64-pin conversion socket (ev-9200g-64) is also provided. prom programmer prom programmer adapter for the m pd75p116gf, connected to the pg-1500. host machines ? pc-9800 series (ms-dos? ver. 3.30 to ver. 5.00a *3 ) ? ibm pc/at? (pc-dos? ver.3.1) ev-9200g-64 hardware software
77 m pd75108f,75112f,75116f document name document number ie-75000-r/ie-75001-r users manual eeuC1455 ie-75000-r-em users manual eeuC1294 ep-75108gf-r users manual eeuC1318 pg-1500 users manual eeuC1335 operation volume eeuC1346 language volume eeuC1343 pg-1500 controller users manual eeuC1291 appendix c. related documents device related documents document name document number users manual iemC1260 instruction application table not available (i) introductory volume iemC1139 (ii) remote control reception volume iemC1281 (iii) barcode reader volume iemC1265 (iv) msk transmission/reception ic control volume iemC1278 75x series selection guide ifC1027 application note development tools documents other documents document name document number package manual ieiC1213 surface mount technology manual ieiC1207 quality grade on nec semiconductor devices ieiC1209 nec semiconductor device reliability & quality control not available electrostatic discharge (esd) test not available semiconductor devices quality guide guarantee guide meiC1202 microcomputer related products guide other manufacturers volume not available note the information in these related documents is subject to change without notice. for design purpose, etc., be sure to use the latest ones. h ra75x assembler package user?s manual hardware software
[memo] m pd75108f,75112f,75116f ms-dos is a trademark of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. m4 92.6 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc.

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